Mr. Nipanka Bora
Electronics and Communication Engineering
Designation: Assistant Professor
PhD (NEHU, Pursuing), M. Tech (Tezpur University)
Specialization: VLSI Design.
Area of Interest: Nano Scaled Device Modeling, CMOS Analog and Mixed Mode Circuit Design.
Mr. Nipanka Bora received his M. Tech degree from Tezpur University in the year of 2010. He is presently working as an Assistant Professor in Electronics and Communication Engineering Department, School of Technology, NEHU, Shillong. Before joining NEHU he worked as Assistant Professor from Nov 2010 to May 2013 at Electronics and Communication Engineering Department, JVW University, Jaipur. Currently he is pursuing PhD from NEHU, Shillong.
Subject Taught/teaching: VLSI Device Modeling, Analog CMOS IC Design, Introduction to VLSI Design etc.
Teaching/Research Experiences: 6 years.
- N. Bora, P. Das, R. Subadar, “An Analytical Universal Model for Symmetric Double Gate Junction- less Transistors”, Journal of Nano- and Electronic Physics, Ukraine, vol. 8, no 2, pp. 02003-02007, 2016.
- R.K. Baruah, N. Bora, “Analytic Solution for Symmetric DG MOSFETs with Gate-Oxide-Thickness Asymmetry”, Journal of Computational and Theoretical Nanoscience , USA, Volume 8, Number 10, October 2011 , pp. 2025-2028(4)
- U. Boro, N. Bora, P. Pegu, R. Subadar, “Impact of Temperature on the Performance of sub- 35nm Symmetric Double Gate Junctionless Transistor based Inverter using high-K Gate Dielectric, a TCAD Simulation Study”, 1st IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES 2016), Delhi Technological University, Delhi, India;
- P. Pegu, N. Bora, U. Boro, R. Subadar, “Performance Evaluation of Dual Material Double Gate Junctionless Field Effect Transistor (DMDG- JLFET) Based Inverter with High-k Spacer and High-k Gate Dielectrics”, International Conference on Engineering Physics, Materials and Ultrasonics (ICEPMU)-2016, The Northcap University, Gurgaon, India.
- N. Bora, P. Das, R. Subadar, “An Analytic potential based Model for Symmetric Double Gate Junction less FETs”, 4th International Conference on Advanced Nanomaterial and Nanotechnology (ICANN-2015), IIT Guwahati, India.
- N. Bora, N. Deka, P.Das, “Drain Current Analytical Model for Undoped Symmetric DG MOSFETs with small Asymmetry in Gate-Oxide-Thickness”, International Conference on Computing and Communication Systems (I3CS’15), NEHU, Shillong 2015.
- N. Bora, P. Das, N. Deka, “Analytical modeling for the drain current of SDG FinFETs including Quantum Mechanical Effects”, ”, International Conference on Computing and Communication Systems (I3CS’15), NEHU, Shillong 2015.
- T. Sharma, N. Bora, ‘Analysis of radiation and parasitic element effects on MOSFETs”, International Conference on Recent Trends of Computer Technology in Academia (ICRTCTA) 2012, J R N Rajasthan Vidyapeeth University, Udaipur, Rajasthan , India .
- N. Bora, R.K. Baruah, "Quantum mechanical treatment on modeling of Drain current, Capacitances and Transconductances for thin film Undoped Symmetric DG MOSFETs", IEEE International Conference on Nanoscience, Technology and Societal Implications (NSTSI 2011), page(s): 1 – 6; Dec 8-10 ,2011, Bhubaneswar.
- N. Bora, R.K. Baruah, “Modeling of thin film SDG MOSFETS with gate oxide thickness Asymmetry”, The International Conference on Communications, Computers and Devices (ICCCD 2010) Dec 10-12,2010, IIT Kharagpur, India.
Participation in Training/Refresher courses/Orientation courses etc.
- Participated in TEQIP national course on “Recent advances in Communications and Signal Processing” from 12-16 Jan, 2015 at IIT Guwahati.
- Organized a 3 Days Workshop on “RF & Microwave Technology for Modern Systems Design” (October 08-10, 2014) at Dept. Of ECE NEHU, Shillong, with support from SAMEER Mumbai.
- Participated in DeitY Workshop on “Multilevel Person Authentication Systems” at Department of Electronics & Communication Engineering, NEHU on 28.09.2013.
- Participated in winter school on “Digital Signal Processing Architectures, Algorithms & Applications” (DSPA++) from 04 - 22 Jan, at IRPEL, Calcutta University Kolkata.
M. Tech Project Supervised: 8
B. Tech Project Supervised: 14 (Approx)