B.Tech (ECE, Kalyani University), M.Tech (ECE, NIT Durgapur), Ph.D. (Pursuing from IIT Kharagpur)
Mixed Signal CAD tool Development
Area of Interest
CAD Tool development for Analog VLSI,Mixed Signal Design, DSP Implementations for FPGA, Antenna Design
Mr. Asif Ahmed received his B.Tech. degree in ECE from MCET Berhampore and his M.Tech degree in Telecommunication Engineering from NIT Durgapur. He had worked at BCET Durgapur from July-2003 as a Lecturer and left as a Senior Lecturer in Jan 2008 and thereafter joined at NIT Durgapur in Feb 2008 as a Project Faculty in Special Manpower Development Project (SMDP-II). After that he joined IIT Kharagpur as a Research Fellow in July 2009 and joined NEHU as Assistant Professor in July 2012.
Electromagnetic Theory, Introduction to VLSI, Electronics Devices and Circuits, Computer Communication and Networks, VLSI Technology, CAD for VLSI, DSP Architectures for VLSI, EDA Tools for VLSI, VLSI Design.
Teaching/Research Experiences:10 years
Participation in Training/Refresher courses/Orientation courses
- Low Power High Speed Digital Subsystem Design-Specs to Test
(7/03/10-13/03/10) at IIT Kharagpur.
- FPGA Laboratory Course (13/07/09-17/07/09) at IIT Delhi.
- Role of soft skills & body language for effective self-projection
(13/10/06 to 14/10/06) from NITTR Kolkata.
- Networking principles & Technology(17/07/06 to 21/07/06)from NITTR Kolkata.
- Teaching Techniques (19/07/05 to 22/07/05) from NITTR Kolkata.
- Recent trends in microwaves & Antennas from NIT Durgapur.
- VLSI Laboratory Course (25/07/06 to 26/07/06) from Asansol Engineering College.
- Qualified in GATE 2002,2003,2005,2006. Scored 96.33 percentile in GATE 2006, Awarded MHRD fellowship for M.Tech and Ph.D.
- I had worked in the India Chip Program where I had designed the 6th order Switched Capacitor Low Pass Filter having a pass-band edge of 110Hz and stop band edge 220 Hz. The intended filter is supposed to work as a sub-module for the bio-pressure sensor chip. We had completed the project successfully ahead of the schedule and the chip was taped out in June2010. This was the first chip from NIT Durgapur and after working in this project I feel pretty much confident to take up similar projects in near future.
M. Tech. Project Supervised
- Implementation of FFT on FPGA using Verilog
- Implementation of 2D-DCT on Spartan-3E FPGA
- FFT Processor using Switched Current Techniques.
B.Tech. Project Supervised
- Matlab Implementation of Floorplanning Toolbox
- Implementation of Lowpass Filter on Stratrix-II FPGA.
- Low Power High Speed OPAMP Design.
- Automated OPAMP Synthesis using Geometric Programming.