• Faculty Coordinator (ECE) of Departmental Carrier Counselling Cell, 2015 to till date.
• Coordinator, M. Tech Project, ECE Department from 2018 to till date.
• Member, Moderation Board for M. Tech (ECE) from 2013 to till date.
• Member, Moderation Board for B. Tech (ECE) from 2013 to till date.
• Member, B. Tech Central Admission Committee of School of Technology (2015 & 2018).
• Member of M. Tech ECE Admission Committee (2013 till date except 2015 and 2018).
• Member, Departmental Purchase Committee, ECE Department from 2013 to till date.
• Member, Departmental Annual Report Committee, ECE Department from 2013 to till date.

Specialization: VLSI Design.

Area of Interest: Nano Scaled Device Modeling, CMOS Analog and Mixed Mode Circuit Design, Nanoelectronics.

Teaching Research Experiences: 12 Years

Publications

Publications Journal:

1. N. Bora*, “An Approach for Drain Current Modeling Including Quantum Mechanical Effects for a DMDG Junctionless Field Effect Nanowire Transistor”, Silicon, vol. 14, pp. 4945–4954 Springer Nature,2022. (SCI- IF 2.94/ Scopus)
2. N. Bora*, N. Deka, R. Subadar, “A Drain Current and Transconductance Analytical Model for Symmetric Double Gate Junctionless FENT”, Journal of Nano Research, vol.65, pp. 39-50, TTP, Switzerland, 2020. (SCI- IF 2.93/ Scopus)
3. N. Bora*, N. Deka, R. Subadar, “A quantum mechanical model of surface potential and drain current for an ultra-short channel double gate junctionless transistor”, Journal of Nano Research, vol.64, pp. 123-134, TTP, Switzerland, 2020. (SCI- IF 2.93/ Scopus)
4. N. Bora*, R. Subadar, “A complete analytical model of surface potential and drain current for an ultra-short channel double gate asymmetric junctionless transistor”, Journal of Nanoelectronics and Optoelectronics, vol. 14, number 9, pp. 1283-1289(7), ASP, USA, 2019. (SCI- IF 1.07/ Scopus) 
5. N. Bora*, R. Subadar, “An analytical surface potential model for highly doped ultrashort asymmetric junctionless transistor”, Advances in Communication, Devices and Networking., LNEE, vol. 537, pp. 45-53, Springer, Singapore, 2019. (Scopus)
6. N. Bora*, R. Subadar, “Performance Analysis of Ultra-Short Junctionless DGMOS Nanowire Transistors with High-k Gate Dielectric”, Journal of Communication Engineering & Systems, vol. 9(1), pp. 35–42, India, 2019.
7. N Bora*, P. Pegu, R Subadar, “A surface potential and threshold voltage model including quantum mechanical effects for a dual material double gate junctionless field effect transistor”, Journal of Advanced Physics, vol. 6, no 3, pp. 408-412, ASP, USA, 2017. (SCI-E)
8. N. Bora*, P. Das, R. Subadar, “An analytical universal model for symmetric double gate junction- less transistor”, Journal of Nano- and Electronic Physics, vol. 8, no 2, pp. 02003-02007, SSUP, Ukraine, 2016. (E-SCI/Scopus)
9. R.K. Baruah, N. Bora, “Analytic Solution for Symmetric DG MOSFETs with Gate-Oxide-Thickness Asymmetry”, Journal of Computational and Theoretical Nanoscience, vol. 8, number 10, pp. 2025-2028(4) ASP, USA, 2011. (SCI- IF 0.91 (2011)/ Scopus)

  Papers presented in Conferences:

1. N. Bora*, A. Sureka, C. Deka, S. Mipun, “Performance analysis of 3-D parallel gated junctionless-field effect nanowire transistor”, Intelligent Computing Techniques for Smart Energy Systems, September 1-3, 2021, Manipal University, Jaipur, India.
2. N. Deka, C. Duari, N. Bora*, “A TCAD simulation-based study of the radiation effects on ultra-thin symmetric double gate-junctionless field effect nanowire transistor (SDG-JLFENT)”, International Conference on Flexible Electronics for Electric Vehicles (FlexEV-2021), March 18-19, 2021, Manipal University, Jaipur, India.
3. K. Jyndiang, N. Bora*, “A charge-based capacitance model for Tri-Gate FinFET”, International Conference on Flexible Electronics for Electric Vehicles (FlexEV-2021), March 18-19, 2021, Manipal University, Jaipur, India.
4. N. Bora*, N. Deka, “A Visual TCAD simulation-based study on the capacitance effects on ultra-thin symmetric double gate (SDG) junctionless field effect nanowire transistor (JLFENT)”, International Web Conference on Recent Advances in Nanoscience & Nanotechnology for High-end Applications (IWCRANHA-2020), 25th -26th July 2020, Assam University, Silchar, India.
5. N. Bora*, R. Subadar, “Performance analysis of ultra-short junctionless DGMOS nanowire transistors with high-k gate dielectric”, 4th National Conference on Emerging Trends and Applications in Computer Science, 2018, Shillong, India.
6. M. R. Hazarika, N. Bora, “Performance analysis of 3-D asymmetric junctionless double gate MOSFET”, IEEE International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS)-2017, Pages 1391-1395, Chennai, India.
7. U. Boro, N. Bora, P. Pegu, R. Subadar, “Impact of Temperature on the Performance of sub- 35nm Symmetric Double Gate Junctionless Transistor based Inverter using high-K Gate Dielectric, a TCAD Simulation Study”, IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES) 2016, Delhi Technological University, Delhi, India.
8. P. Pegu, N. Bora, U. Boro, R. Subadar, “Performance evaluation of Dual Material Double Gate Junctionless Field Effect Transistor (DMDG-JLFET) based inverter with high-k spacer and high-k gate dielectrics”, International Conference on Engineering Physics, Materials and Ultrasonic (ICEPMU) 2016, The Northcap University, Gurgaon, India.
9. N. Bora*, P. Das, R. Subadar, “An Analytic potential based Model for Symmetric Double Gate Junction less FETs”, 4th International Conference on Advanced Nanomaterial and Nanotechnology (ICANN) 2015, IIT Guwahati, India.
10. N. Bora*, N. Deka, P. Das, “Drain Current Analytical Model for Undoped Symmetric DG MOSFETs with small Asymmetry in Gate-Oxide-Thickness”, International Conference on Computing and Communication Systems (I3CS) 2015, NEHU, Shillong India.
11. N. Bora*, P. Das, N. Deka, “Analytical modeling for the drain current of SDG FinFETs including Quantum Mechanical Effects”, International Conference on Computing and Communication Systems (I3CS) 2015, NEHU, Shillong, India.
12. T. Sharma, N. Bora, ‘Analysis of radiation and parasitic element effects on MOSFETs”, International Conference on Recent Trends of Computer Technology in Academia (ICRTCTA) 2012, J R N Rajasthan Vidyapeeth University, Udaipur, Rajasthan, India.
13. N. Bora*, R.K. Baruah, "Quantum mechanical treatment on modeling of Drain current, Capacitances and Transconductances for thin film Undoped Symmetric DG MOSFETs", IEEE International Conference on Nanoscience, Technology and Societal Implications (NSTSI 2011), page(s): 1 – 6; Dec 8-10 ,2011, Bhubaneswar, India.
14. N. Bora*, R.K. Baruah, “Modeling of thin film SDG MOSFETS with gate oxide thickness Asymmetry”, The International Conference on Communications, Computers and Devices (ICCCD 2010) Dec 10-12,2010, IIT Kharagpur, India.

Research Papers Reviewed for Journals: (Selected)

• Silicon, (Springer Nature, Netherlands).
• Journal of Nano Research (Trans Tech Publications, Switzerland).
• Journal of Nanoscience and Nanotechnology (American Scientific Publisher, USA).
• Journal of Nanoelectronics and Optoelectronics (American Scientific Publisher, USA).

Any other:

• B. Tech. Project Supervised: More than 25.
• M. Tech Project Supervised: More than 16.